Published papers

Update: Nov 8th, 2009

In the third year of University I worked on the CREC project. CREC stands for Calculator REConfigurabil which would be translated as Reconfigurable Computer.

“The main research done in the field of Reconfigurable Computing was oriented towards applications involving low granularity operations and high intrinsic parallelism. CREC is an original, low-cost general-purpose Reconfigurable Computer whose architecture is generated through a Hardware / Software CoDesign process. The main idea of the CREC system is to generate the best-suited hardware architecture for the execution of each software application. The CREC Parallel Compiler parses the source code and generates the hardware architecture, based on multiple Execution Units. The hardware architecture is described in VHDL code, generated by a program. Finally, CREC is implemented in an FPGA device. The great flexibility offered by the general-purpose CREC system makes it interesting for a wide class of applications that mainly involve high intrinsic parallelism, but also any other kinds of computations.”

During this project I was a co-author on several published papers:

The project was interesting and gave me a chance to learn a bit about the mystical world of parsers and compilers. The most useful trade I learned was probably regular expressions. The work was interesting but I must say I disagreed to the concept of a general purpose computer. I strongly believed back than that a specialized processor would be a better suited application for the project.

My long term idea for the project was to build a reconfigurable coprocessor for a general computing architecture (like the x86). Bundled with a smart firmware (a hypervisor type software?) , the system could identify repetitive tasks and recompile them to a parallel architecture which in term would offload the main processor. Not sure if this would have been possible automatically but another option could have been to provide a high level API which would allow a software to explicitly offload tasks to the parallel coprocessor.

The processor would have been well suited for several tasks like:

  • compression/encryption
  • video/still image processing
  • TCP offloading (or maybe a high performance iSCSI initiator/target)
  • Graphics processor/accelerator

Using my concept of a API driven parallelization I suspect that whole applications could have been offloaded to the parallel coprocessor. How about a high performance web server that creates a new processor/”processing unit” per client?

However it seems the industry took another turn, they are still using parallel processors but just put a lot of pre-configured processing units (called cores these days) that do the job. The above concept might still be feasible for very specific applications but the price point of general purpose cores is so low that the problem lies somewhere else: the software. It’s difficult to write parallel software (especially if the branches are not fully independent) and it’s even more difficult to write parallelizing compilers. This is something that I attempted back then and came up with a very basic compiler for a C like language that could identify independent sequential instructions. This is as far as I got back than.

I am wondering if anyone in the industry implemented something similar to my concept, I would enjoy reading about the challenges and the solutions.

Acknowledgments

This research was supported by the Romanian Ministry of Research, Education and Youth, National University Research Council, under the AT grant, theme 140 / 2003.

Reblog this post [with Zemanta]
No comments yet.